Search - verilog sdram

[VHDL-FPGA-Verilog] sdram_src

Description: 基于FPGA的读写控制，sdram，简单易懂，verilog代码描述-FPGA-based read and write control, sdram, easy to understand, verilog code Description
Platform: | Size: 10240 | Author: 张红玉 | Hits:

[VHDL-FPGA-Verilog] SDRAM_Verilog

Description: 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
Platform: | Size: 3072 | Author: zhanglong | Hits:

[VHDL-FPGA-Verilog] sdram_singale_word

Description: 使用verilog驱动的sdram单字节读写，可以学习一下sdram最基本的功能，学习sdram参考程序。-Use sdram verilog-driven single-byte read and write, you can learn the most basic functions sdram, sdram reference learning program.
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] sdram_mdl

Description: 基于SDRAM的读写调试试验，使用verilog语言编写，经过调试。-SDRAM-based literacy commissioning tests, using verilog language, through debugging.
Platform: | Size: 2285568 | Author: jianglei | Hits:

[source in ebook] SDRAM_interface

Description: SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a refresh timer)
Platform: | Size: 2048 | Author: bryan | Hits:

[VHDL-FPGA-Verilog] sdram_5

Description: SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog description, including top-level design, testbench code, an accurate description of
Platform: | Size: 6144 | Author: micheal zhang | Hits:

[VHDL-FPGA-Verilog] SDRAM_96M

Description: 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even on the serial port, the data will have to go under, 9600 baud, one stop bit, SDRAM clock is 96MHz, automatically generated data FPGA the correct result is output to the FF 00 is incremented by one, recycle. The project is relatively small warning, a warning is intentionally basic timing also has converged.
Platform: | Size: 5591040 | Author: Grace | Hits:

[Other] sdram_top

Description: 使用FPGA实现SDRAM逻辑控制器，适用于各种型号的FPGA-SDRAM control by verilog
Platform: | Size: 204800 | Author: 贾先生 | Hits:

[Driver Develop] S27_SDRAM_IP

Description: SDRAM 驱动读写demo，用verilog写的上板测试过-SDRAM verilog
Platform: | Size: 6847488 | Author: 夜星辰 | Hits:

[VHDL-FPGA-Verilog] ALTERA_FPGA_SDRAM

Description: 使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
Platform: | Size: 13050880 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] 5_Gray_Mean_Filter

Description: 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有：（1）带PLL的全局时钟管理模块 system_ctrl_pll.v （2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig （3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 （4）SDRAM数据交互控制器Sdram_Control_2Port （5）VGA时序驱动电路lcd_driver -Design the required modules are: (1) global with PLL clock management module system_ctrl_pll. V. (2) the OV7725 COMS i2c_timing_ctrl initialization module, I2C_OV7725_RGB565_Conofig Sensor (3) the OV7725 COMS Sensor COMS_Capture_RGB565 video signal acquisition module (4) SDRAM controller data interaction Sdram_Control_2Port (5) the VGA timing drive circuit lcd_driver 逐句翻译
Platform: | Size: 8895488 | Author: Keyonwho | Hits:

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